Architecture - Architecture ASIC / System (ASIC Design)

TL;DR

Architecture - Architecture ASIC / System (ASIC Design): Designing and implementing forward error correction (FEC) and DSP schemes for optical coherent transceivers using hardware description languages (HDL) for ASICs with an accent on reliability and validation of these hardware blocks. Focus on analysis and implementation of state-of-the-art error correction techniques, including floating- and fixed-point simulation platforms and HDL (Verilog/SystemVerilog) implementation.

Location: Cordoba, Argentina

Company

hirify.global is a semiconductor company providing essential building blocks for data infrastructure across enterprise, cloud, and AI.

What you will do

• Design and implement forward error correction (FEC) and DSP schemes for optical coherent transceivers.
• Implement hardware blocks in ASICs using Hardware Description Languages (HDL).
• Ensure reliability and validation of hardware blocks.
• Analyze state-of-the-art error correction techniques.
• Utilize floating- and fixed-point simulation platforms for analysis.

Requirements

• Engineering degree in electronics, computer software, or telecommunications.
• Proven experience in C, C++, Verilog, SystemVerilog, and Python programming.
• Good written and oral communication skills.
• Applicants must be eligible to access export-controlled information as defined under U.S. export control laws and regulations.

Nice to have

• Prior experience in advanced digital architectures design and testing.

Culture & Benefits

• Competitive compensation and great benefits.
• Workstyle with shared collaboration, transparency, and inclusivity.
• Tools and resources for success and professional development.
• Commitment to fair and authentic hiring practices; AI tools are not permitted during interviews.