Lead Design Verification Engineer

TL;DR

Lead Design Verification Engineer: Architecting and delivering next-generation chassis IPs by establishing comprehensive verification strategies and methodologies. Focus on designing and implementing advanced verification environments, ensuring first-pass silicon success through deep expertise in interconnect protocols, cache coherency, and memory architecture.

Location: US, California, Santa Clara. This role will require an on-site presence.

Salary: $220,920.00-311,890.00 USD

Company

hirify.global is a data-driven organization building scalable engineering solutions across product enablement, custom ASIC, and foundry enablement, focused on customer-driven, end-to-end solutions.

What you will do

• Architect, develop, and deliver comprehensive verification strategies and methodologies for IP to SoC-level.
• Design and implement advanced verification environments, tools, and testplans.
• Collaborate closely with architecture, design, and software teams from product definition through productization.
• Drive ownership of multiple critical blocks and verification components, ensuring functional signoffs and achievement of performance and power metrics.
• Lead IP delivery to multiple customers while ensuring technical excellence.
• Champion innovation across simulation, formal, and accelerated verification methodologies.

Requirements

• 14+ years of relevant experience in design verification, with significant background in IP DV and subsystem/SoC-level verification.
• Proven deep expertise in interconnects, caches, and memory subsystems, including multiple bus protocols such as AMBA (CHI, ACE, AXI), PCIe, UCIe, and CXL.
• Demonstrated experience in verification of global functions including debug, trace, clock and power management, RAS, QoS, and security features.
• Strong background in simulation-based verification methodologies including UVM, ABV, and co-simulation; proficiency in low-power verification techniques, HDL/verification languages, and industry-standard EDA tools.
• Advanced hands-on coding proficiency across SystemVerilog/UVM, software programming languages (C/C++), and scripting (Python).
• Demonstrated experience collaborating with formal verification and emulation teams to develop multimodal verification strategies.

Culture & Benefits

• Competitive total compensation package that ranks among the best in the industry, including competitive pay, stock bonuses, and benefit programs.
• Health, retirement, and vacation benefits available.
• Opportunities for mentorship and development of verification engineers.
• Commitment to Responsible Business Alliance (RBA) compliance and ethical hiring practices.