TL;DR

ASIC Design Engineer: Developing, implementing, and testing high-performance communications/networking ASIC products with an accent on RTL design, verification, synthesis, and static timing analysis. Focus on block/chip level design and integration, solving complex design tradeoffs, and ensuring robust high-volume manufacture.

Location: Onsite, Varna, Bulgaria

Company

%hirify_global% is a global technology leader that designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions.

What you will do

Work closely with marketing, architecture, firmware, physical, and layout teams on the full product development cycle from definition to production.
Involve in engineering implementation spec writing from marketing/system requirements.
Perform RTL design and verification.
Execute synthesis and static timing analysis.
Be responsible for block and/or chip level design and integration.

Requirements

BSEE/MSEE with a minimum of 8 years of experience developing, implementing, and testing high-performance communications/networking ASIC products.
Strong understanding of system design tradeoffs for high volume applications.
Good RTL experience including specification, design, verification, and synthesis.
Strong UNIX-based EDA tool skills and knowledge of ASIC design flows.
Familiarity with reusable HDL coding styles and design for high volume manufacture.
Proficiency in Verilog/VHDL coding and Lint tools.
Experience with Synthesis and Timing Analysis using Synopsys tool suite (Synopsys Primetime).
Knowledge of Formal Verification and DFT concepts of Scan, BIST.
Strong Perl and Tcl scripting skills.

Culture & Benefits

%hirify_global% is an equal opportunity employer.