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5 дней назад

Lead Mixed Signal Design Verification Engineer (Hardware)

Формат работы
onsite
Тип работы
fulltime
Грейд
lead
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR

Lead Mixed Signal Design Verification Engineer (Hardware): Defining verification plans, models, and roadmaps and delivering complete Mixed-Signal DV solutions across diverse mixed-signal products with an accent on driving innovation across the Mixed-Signal verification flow to create efficient and accurate mixed-signal methodologies. Focus on architecting, developing, and implementing metric-driven mixed-signal verification solutions and pushing technology for mixed-signal modeling and simulation to improve efficiency and accuracy.

Location: Cary, San Jose, or Austin, USA

Company

hirify.global hires and develops leaders and innovators impacting the world of technology, specializing in electronic design automation.

What you will do

  • Architect and implement metric-driven mixed-signal verification solutions, including digital/DMS/AMS testbench creation, automatic model generation, and mixed-signal VIP integration.
  • Drive innovation in mixed-signal modeling, simulation, and DV to improve verification efficiency and accuracy.
  • Ensure scalable mixed-signal DV solutions for IPG offerings like SerDes, DDR, and A2D converters.
  • Develop efficient debug solutions and a full-stack mixed-signal methodology for the entire IP stack.
  • Propagate mixed-signal knowledge, mentor junior engineers, and collaborate with various engineering and support teams.

Requirements

  • 4+ Years’ experience in Digital and Analog mixed-signal environments and teams.
  • Good written and verbal cross-functional communication skills.
  • Proven experience in creating verification infrastructure, scripting verification flows, and debugging test cases.
  • Knowledge of existing and upcoming standards such as PCIE, USB, and DDR4.
  • Comfortable interacting across the IPG development team and understanding design constraints.
  • Bachelor's Degree (MSEE/PhD Preferred).

Nice to have

  • Knowledge of multiple programming languages (C++, Python, System Verilog, e).
  • Familiarity with Mixed-Signal hirify.global tools and methodologies.
  • Working knowledge of System Verilog and UVM Test environment/methods.
  • Experience with revision control tools like SOS, SVN.

Culture & Benefits

  • Focus on hiring and developing leaders and innovators.
  • Opportunity to impact the world of technology.
  • Collaborative environment across engineering teams.
  • Mentoring opportunities for junior engineers.
  • Solving complex technical challenges.

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