Principal Soc Architect (Ml Accelerators)

TL;DR

Principal SoC Architect (ML Accelerators): Defining architectures and design tradeoffs of ML-centric SoCs that fuse analog precision, digital signal processing, and embedded machine learning with an accent on compute fabrics, dataflows, memory hierarchies, and integration with mixed-signal front ends. Focus on prototype breakthrough architectures, validate them in real-world scenarios, and chart the path to scalable silicon implementation.

Location: Hybrid in Austin, Texas. Candidates for this role must be able to access technical data without a requirement for an export license. We are unable to sponsor or obtain export licenses for this role.

Company

hirify.global solves complex challenges with innovative end-user solutions for the world's top consumer brands.

What you will do

• Define the end-to-end architecture for ML accelerators and SoCs, including compute fabrics, dataflows, memory hierarchies, and integration with mixed-signal front ends.
• Translate domain-specific requirements into architectural specifications and accelerator designs.
• Lead architectural exploration of performance, power, area, and cost tradeoffs; create models and benchmarks for workload-driven analysis.
• Collaborate closely at the instruction set and compiler/toolchain level to ensure that the ISA, micro-architecture, and runtime stack are co-optimized for ML workloads and domain-specific kernels.
• Partner with internal engineering, startups, and research institutions to rapidly prototype candidate architectures on FPGA/ASIC platforms and validate with representative workloads.
• Define and evaluate on-chip security architectures, including trusted execution environments (TEE), enclaves, memory partitioning, and hardware root-of-trust, ensuring robust protection for ML-enabled SoCs.

Requirements

• Ph.D or Master’s degree in Electrical Engineering, Computer Engineering, or related technical field.
• 10+ years in SoC or accelerator design, with a focus on ML, DSP, or high-performance edge compute.
• Deep understanding of ML accelerator architectures, including systolic arrays, SIMD/VLIW, RISC-V/ARM integration, memory subsystems, and dataflow optimization.
• Hands-on experience defining ISAs or ISA extensions and collaborating with compiler/runtime teams to tightly couple software to hardware micro-architecture.
• Familiarity with the architectural implications of coupling ML compute with analog/mixed-signal front ends.

Nice to have

• Experience in hardware-level security stacks, including TEEs, enclaves, memory isolation schemes, secure boot, and cryptographic accelerators.
• Experience driving early-stage architectural concepts from exploration through to prototype.
• Expertise in energy-efficient architectures for edge workloads.
• Strong network in academia and industry in ML accelerators, SoC design, or edge AI.

Culture & Benefits

• Award-winning culture built on inclusion and fairness.
• Meaningful community engagement.
• Enjoyable employee experiences.
• Opportunity to solve complex challenges with innovative end-user solutions for the world's top consumer brands.