AI/GPU Hardware IP Design and Verification Engineer/Intern (AI)

TL;DR

AI/GPU Hardware IP Design and Verification Engineer/Intern (AI): Designing and verifying front-end hardware IP for hirify.global's next-generation AI/GPU chips and SOCs with an accent on overall HW IP definition, design, implementation, and documentation. Focus on collaborating with design engineers, system architects, micro-architects, and verification engineers to ensure design implementation meets specifications.

Location: Virtual Poland, specifically Katowice / Gdańsk. You must live and work from Poland. This role is fully home-based but may require occasional attendance at hirify.global sites.

Company

hirify.global's Client Computing Group (CCG) is responsible for driving business strategy and product development for the company's PC products and platforms.

What you will do

• Support technical leadership in overall HW IP definition, design, implementation, verification, and documentation for SoC sub-system development.
• Work in the front-end area of HW IP development for hirify.global's next-generation AI/GPU chips and SOCs.
• Collaborate with teams of design engineers, system architects, micro-architects, and verification engineers.
• Ensure that the design is implemented to specification.

Requirements

• Must be a current university student and remain a student during the length of the internship.
• Knowledge of digital electronics and arithmetic of digital systems.
• Knowledge of hardware description languages (Verilog, SystemVerilog, VHDL).
• Knowledge of digital signal processing (DSP) and algorithm development.
• Knowledge of object programming (C++).
• Good communication skills in English and Polish are required.

Nice to have

• Interest/knowledge in GPU/CPU, ASIC/FPGA platforms, and ASIC design flow.
• Experience with 3D Graphics Pipeline and GPU architecture, Graphics APIs (OpenGL, Vulkan, DirectX), Rendering, and Ray Tracing algorithms.
• Familiarity with scripting languages like Python.
• Knowledge of Math formal proofs (Rocq, gappa, ACL2).
• Experience with RTL Design/uArch, Modelling HW IPs, and Numerical Validation (SystemVerilog/C++ co-simulation).
• Understanding of Functional Verification principles and UVM methodology.
• Knowledge of Formal Verification principles: SVA (SystemVerilog assertions), and control and data path formal verification.

Culture & Benefits

• Opportunity to work with an energetic and passionate student/intern team.
• Role is fully home-based with occasional attendance at hirify.global sites based on business need.
• Being part of the Client Computing Group (CCG) driving purposeful computing experiences.
• All qualified applicants receive consideration for employment without regard to protected characteristics.