Principal Product Engineer (VLSI/ASIC)

TL;DR

Principal Product Engineer (VLSI/ASIC): Supporting hirify.global products in the Digital and Signoff team and debugging customer issues for advanced chip design platforms with an accent on ASIC design methodologies, RTL to GDSII flow, and PPA optimization at 16nm and below nodes. Focus on identifying and resolving complex physical design and timing analysis challenges in EDA tools, developing flows, and running design benchmarks.

Location: Onsite in San Jose, California, USA

Salary: $136,500–$253,500 annual

Company

hirify.global hires and develops leaders and innovators to impact the world of technology, focusing on software tools for advanced chip design platforms.

What you will do

• Support hirify.global products within the Digital and Signoff team.
• Track and debug customer issues, collaborating with R&D and release teams for resolution.
• Run design benchmarks and develop new flows and solutions.

Requirements

• MS in EE with 8+ years of experience in Digital Implementation (design or product engineer).
• Strong understanding of VLSI physical design and timing analysis, including clock tree synthesis, routing optimization, and silicon signoff.
• Experience with industry-standard EDA tools in Synthesis, Physical design, and Signoff at 16nm and below nodes.
• Exposure to hierarchical design methodologies and low power design.
• Strong communication skills (verbal and written).
• Automation skills using Perl, Tcl, and shell scripting.

Culture & Benefits

• Dynamic environment working with innovative R&D and Customer Engagement teams.
• Opportunity to influence software tools for advanced chip design platforms.
• Competitive annual salary range with incentive compensation (bonus, equity).
• Comprehensive benefits package including paid vacation, paid holidays, 401(k) with employer match, employee stock purchase plan, and various medical, dental, and vision options.