Senior Staff Engineer (Digital IC Design)

TL;DR

Senior Staff Engineer, Digital IC Design (ASIC): Responsible for post-RTL design flow, including block/chip level synthesis, timing closure, DFT generation, and ECOs for SerDes PHY solutions. Focus on improving design methodology, collaborating with Analog/Digital design teams, and supporting pre and post-silicon product teams.

Location: Onsite in Hsinchu, Taiwan

Company

hirify.global is a semiconductor company providing essential building blocks for data infrastructure across enterprise, cloud, and AI architectures.

What you will do

• Improve the design methodology and flow.
• Perform synthesis, timing closure, and DFT support for various types of SerDes IPs (10Gbps to 224Gbps).
• Collaborate with Analog/Digital design teams to deliver competitive SerDes IP solutions.
• Provide support to product teams for both pre and post-silicon activities.

Requirements

• Master’s degree and/or PhD in EE, CS or related fields and 6+ years of experience.
• Must have good post-RTL experience including synthesis, timing analysis, and physical design.
• Able to perform custom placement and routing for mixed-signal designs.
• Proficient in logic or physical synthesis using Synopsys or Cadence tools.
• Proficient in DFT generation and verification, and static timing analysis using Primetime.
• Strong Perl and Tcl scripting skills.

Culture & Benefits

• Competitive compensation and benefits within an environment of shared collaboration, transparency, and inclusivity.
• Dedicated to providing tools and resources for people to succeed and grow.
• All qualified applicants will receive consideration for employment without discrimination.
• Interviews are designed to evaluate individual experience, thought process, and communication skills in real time.