SEV Validation Senior Staff Engineer (SerDes)

TL;DR

SEV Validation Senior Staff Engineer (SerDes): Building and optimizing silicon/system electrical validation infrastructure with an accent on high-speed I/O (SerDes) post-silicon validation, L1/L2 Ethernet layers, and PCIe protocols. Focus on designing scalable validation test infrastructure, debugging complex system-level problems, and utilizing advanced lab equipment.

Location: Yokneam

Company

hirify.global’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world.

What you will do

• Develop, implement, and analyze the execution and results of silicon/system validation.
• Design and build scalable validation test infrastructure, including hardware setups, software frameworks, and automation tools.
• Execute hands-on test and validation of analog/digital & signal/power integrity using lab equipment.
• Debug and solve system-level problems, leveraging strong analytical skills and lab experience.

Requirements

• Bachelor’s/Master’s degree in Electrical Engineering, Computer Science or related fields.
• 5-20 years of related professional experience in silicon/system electrical validation (or 10+ years with Bachelor's, 3-5 years with Master's/PhD).
• Strong understanding of high-speed SERDES, equalization technique, and PCIe protocols.
• 5+ years experience with High Speed IO testing, debugging, and validation.
• Strong lab skills with hands-on experience in system bring up, system testing, and debug.
• In-depth working knowledge of test equipment used for SERDES characterization (Scope, BERT, Network analyzer, etc.).
• Scripting skills in one or more programming languages, Python is an advantage.

Nice to have

• Experience in definition and implementation of a validation automation test infrastructure.
• Capability of implementing hardware test automation.
• Working knowledge of PCIe interface and characterization.
• Working knowledge and experience on Ethernet and/or SAS/SATA SERDES.
• Extensive knowledge of the physical and protocol levels of one or more common high-speed interfaces.
• Working knowledge of board design; able to read board schematics and layout.
• Knowledge in SERDES modeling techniques.

Culture & Benefits

• Competitive compensation and great benefits with an environment of shared collaboration, transparency, and inclusivity.
• Dedicated to giving employees the tools and resources needed to succeed and grow.

Hiring process

• Candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
• Use of AI tools without prior instruction from the interviewer will result in disqualification.
• This position may require access to technology and/or software subject to U.S. export control laws and regulations.
• Applicants must be eligible to access export-controlled information; non-U.S. citizens/permanent residents/protected individuals may be subject to an export license review process.