Senior Principal Digital IC Design Engineer (Semiconductor)

TL;DR

Senior Principal Digital IC Design Engineer (Semiconductor): Designing and implementing world-class ASICs for high-performance communication products with an accent on SoC-level specifications, RTL development, and integration. Focus on collaborating with architecture teams, defining micro-architecture specifications, and leading complex design reviews.

Location: Santa Clara, CA

Salary: $168,920–$253,000 per annum

Company

hirify.global provides semiconductor solutions that are essential building blocks for data infrastructure across enterprise, cloud, and AI.

What you will do

• Collaborate with systems and architecture teams to define SoC-level specifications.
• Translate high-level product requirements into detailed micro-architecture specifications.
• Lead RTL development and integration, ensuring modularity, reusability, and design compliance.
• Partner with DV teams to define and review comprehensive verification plans.
• Support pre-silicon bring-up and post-silicon validation activities with lab teams.
• Supervise and mentor junior digital design engineers, providing technical leadership.

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering, or related fields with 15+ years of professional experience, or Master’s/PhD with 10+ years of experience.
• Minimum of 10 years of industry experience in developing, implementing, and testing high-performance communications ASIC products.
• Extensive experience in RTL design, including verification, synthesis, and timing closure.
• Strong background in embedded microcontroller systems.
• Proficiency with UNIX-based EDA tools (e.g., VCS, PrimeTime, Design Compiler, CDC) and deep understanding of ASIC design flows.
• Familiarity with PHY/MAC layer communication protocols such as Ethernet, PCIe, UA Link, SUE, or ESUN.
• Applicants must be eligible to access export-controlled information as defined under U.S. export control laws and regulations.

Nice to have

• Knowledge of signal processing circuit structures or error-correcting code architectures.
• Experience with industry-standard interfaces such as MDIO, I2C, I3C, SPI, and SMBus.

Culture & Benefits

• Comprehensive total compensation package including base, bonus, and equity.
• Health and financial wellbeing benefits, including flexible time off and 401k.
• Additional perks such as a year-end shutdown, floating holidays, and paid time off to volunteer.
• Opportunity to thrive, learn, and lead in an environment that values innovation, transparency, and execution.

Hiring process

• Candidates are asked not to use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT) during interviews.
• Use of such tools during an interview will result in disqualification from the hiring process.