PCIe/CXL Architect (IoT Hardware)

TL;DR

Principle PCIe/CXL Design Engineer (Hardware): Defining and implementing micro-architectures for state-of-the-art datacenter and AI SOCs with an accent on PCIe/CXL subsystem design, RTL coding, and cross-functional team collaboration. Focus on delivering high-quality hardware, ensuring timing signoff, and resolving post-silicon lab issues.

Location: Onsite in one of the following US locations: Westborough, MA; Irvine, CA; Austin, TX; Santa Clara, CA; Morrisville, NC. Applicants must be eligible to access export-controlled information under U.S. law, which may require U.S. citizenship, lawful permanent residency, or protected individual status.

Salary: $204,900 – $303,250 per annum

Company

hirify.global provides semiconductor solutions that serve as essential building blocks for data infrastructure across enterprise, cloud, and AI architectures.

What you will do

• Define the micro-architecture of PCIe/CXL subsystems for datacenter and AI SOCs.
• Collaborate closely with architecture, floor planning, backend, verification, DFT, and STA teams.
• Develop and write micro-architectural specifications for designs.
• Implement designs using good RTL coding and low power techniques.
• Collaborate with the backend team for synthesis, place and route, and timing signoff.
• Work with the verification team on pre-silicon tasks and the post-silicon group for lab issue resolution.

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering, or related fields with 15+ years of professional experience (or Master’s with 12+ years, or PhD with 10+ years).
• Expertise in PCIe/CXL architecture, micro-architecture, and translating requirements into design.
• Expertise in interacting with 3rd party IP vendors and customers.
• Expertise in System Verilog RTL coding techniques.
• Familiarity with modern PCIe and SoC architectures and various interface technologies (AXI, CXL, IDE, TDISP, ATS, LTSSM, VDM, MSI-X).
• Experience in RTL design, synthesis, static-timing closure, formal verification, gate-level simulations, and block-level functional verification.
• Experience in implementation/timing closure for high-speed design.
• Applicants must be eligible to access export-controlled information as defined under applicable U.S. law.

Nice to have

• Hands-on experience with front-end design tools and methodologies.
• Knowledge of scripting languages such as Python, Perl, Tcl, and UNIX shell.

Culture & Benefits

• Comprehensive benefits supporting financial well-being, family support, mental/physical health, and recognition.
• Employee stock purchase plan with a 2-year look back.
• Family support programs and robust mental health resources.
• Commitment to providing consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Hiring process

• Candidates are not permitted to use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
• Use of AI tools without prior instruction from the interviewer will result in disqualification.