SYN/STA Engineering Intern (Optical PHY)

TL;DR

SYN/STA Engineering Intern (Optical PHY): Designing circuits for high-speed optical transceivers for communication infrastructure with an accent on logic synthesis, static timing analysis, and ASIC/SoC designs. Focus on learning and applying industry-standard EDA tools and scripting for design correctness and timing closure.

Location: Onsite in Ho Chi Minh, Vietnam

Company

hirify.global is a semiconductor solutions company providing essential building blocks for data infrastructure across enterprise, cloud, AI, and carrier architectures.

What you will do

• Perform logic synthesis and static timing analysis (STA) at sub-system or top level for multi-million gate ASIC projects.
• Ensure design correctness and quality through RTL Lint, CDC, LEC, and functional ECO.
• Achieve timing closure using constraint validation, STA signoff, and timing ECOs.
• Collaborate with logic design (RTL) and physical design (PD) engineers to resolve design, timing, power, and physical implementation issues.
• Assist with schedule management and support cross-functional engineering efforts.
• Contribute to the development, enhancement, and maintenance of Synthesis and STA scripts and automation flows.

Requirements

• Currently pursuing 3rd or 4th year of BS in Electrical Engineering/Computer Engineering, or related fields, with knowledge of digital design.
• Solid foundation knowledge of logic synthesis and static timing analysis (STA) for ASIC/SoC designs.
• Familiar with ASIC design flows, including Front-End design, DFT, and Physical Design (PnR).
• Familiar with industry-standard EDA tools, including logic synthesis (Synopsys DC, Cadence Genus), logical equivalence checking (Formality, Conformal), and STA (PrimeTime, Tempus).
• Proficiency in programming and scripting with PERL/Python, TCL, and C/C++ in a Unix-based environment.
• Confident in written and verbal English communication skills.

Nice to have

• Experience in RTL coding and Design verification.
• Knowledge of DFT methodologies.
• Experience with SERDES, Data Communication, and Ethernet protocols.

Culture & Benefits

• Gain real project experience in a leading chip design environment.
• Get exposure to hirify.global’s core technologies, toolchains, and product workflows.
• Benefit from a mentorship path that could evolve into a full-time role or thesis opportunity.
• Enjoy competitive compensation and great benefits.
• Work in an environment of shared collaboration, transparency, and inclusivity.