CAD Engineer (AI)

TL;DR

CAD Engineer (AI): Developing AI-driven automation for ASIC design flows and tools, integrating cutting-edge AI capabilities into full-stack web/linux applications to improve efficiency and performance. Focus on designing and optimizing AI algorithms for hardware-assisted environments, building APIs, and performing system-level testing and analysis.

Location: Santa Clara, CA. Eligibility to access U.S. export-controlled information is required.

Salary: $105,470–$158,000 per annum

Company

hirify.global is a semiconductor company providing essential building blocks for data infrastructure across enterprise, cloud, and AI architectures.

What you will do

• Design and develop AI-driven full-stack web applications.
• Collaborate with cross-functional teams to integrate web-based solutions.
• Develop and optimize AI algorithms and models for hardware-assisted environments.
• Build APIs and backend systems to support AI functionalities within web applications.
• Perform system testing, debugging, and performance/regression analysis on developed applications.
• Stay current with emerging AI technologies, CAD innovations, and advancements in ASIC design processes.

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and at least 1-3 years of related professional experience or Master’s degree.
• Familiarity with AI/ML model development and deployment.
• Proven experience in web/linux UI and CLI application development.
• Proficiency in modern web technologies (JavaScript, HTML, CSS, React, Angular, Django, Node.js) and programming (Python, C++, PHP, TCL, JavaScript).
• Familiarity with AI-based development assistants and code generators (e.g., GitHub Copilot, Grok, GPT, Gemini, Claude).
• Familiarity with CAD tool development or ASIC design projects.
• Eligibility to access U.S. export-controlled information is required.

Nice to have

• Experience with EDA tools and ASIC design processes (Synthesis, LEC, P&R).
• Solid understanding of design sign-off processes (STA, DRC, LVS, ERC, EMIR).
• Experience with advanced technology nodes (n5/n3/n2) design process.
• Knowledge of hardware description languages (Verilog/VHDL).

Culture & Benefits

• Total compensation package with a base, bonus, and equity.
• Health and financial wellbeing are part of the package (flexible time off, 401k, year-end shutdown, floating holidays, paid time off to volunteer).

Hiring process

• Candidates must not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT) during interviews.
• Usage of such tools during an interview will result in disqualification from the hiring process.