Senior Pre-Silicon Verification Engineer (Mixed-Signal Verification)

TL;DR

Senior Pre-Silicon Verification Engineer (Mixed-Signal Verification): Developing comprehensive verification strategies for digital and mixed-signal IP blocks, creating advanced behavioral models, and executing thorough verification plans with an accent on functional, performance, and power requirements across hirify.global's cutting-edge semiconductor designs. Focus on modeling analog-digital interactions, validating designs across PVT variations, and debugging complex issues in the pre-silicon environment.

Location: On-site in Toronto, Canada

Salary: CAD 153,910–217,280

Company

hirify.global is a leading global technology corporation inventing at the boundaries of technology to create amazing experiences for business and society.

What you will do

• Perform functional verification of digital and mixed-signal logic components, including analog behavioral modeling and advanced verification techniques (UVM, AMS simulation).
• Develop comprehensive IP verification plans, test benches, and scalable verification environments for mixed-signal microarchitecture specifications.
• Execute verification plans, analyze power/timing/performance metrics, and conduct system-level simulations and corner case analysis.
• Replicate, root cause, and debug complex issues in the pre-silicon environment, implementing corrective measures.
• Collaborate with digital and analog architects, RTL developers, and physical design teams to meet functional, performance, and power goals.
• Document test plans, drive technical reviews, and maintain/improve verification infrastructure and methodology.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a STEM related field of study.
• 5+ years of experience in digital design verification or mixed-signal verification.
• 3+ years of experience with Pre-Silicon Verification environment architecture and development.
• Experience with complex mixed-signal IP verification or system-level verification.
• Experience in both digital verification methodologies (UVM/SystemVerilog).
• Experience with Perl, HTML, or Python scripting (Python preferred).

Nice to have

• Master's degree in Electrical Engineering, Computer Engineering, or a STEM related field of study.
• Experience with working in mixed-signal design like SerDes or PLLs, including SerDes PHY verification.
• Experience driving verification methodology changes and initiatives.
• Experience with Mixed Signal Verification (MSV) and Gate Level Simulation (GLS).
• Experience with concepts of DFT, ATE, HVM.

Culture & Benefits

• Competitive salary and comprehensive benefits package.
• Opportunity to work on hirify.global's most advanced mixed-signal designs and technologies.
• Access to cutting-edge mixed-signal verification tools and simulation infrastructure.
• Collaboration with world-class analog and digital design engineers and architects.
• Professional development opportunities in advanced mixed-signal verification techniques.
• Direct impact on hirify.global's leadership in mixed-signal semiconductor innovation.