Mixed Signal Modelling And Verification Engineer

TL;DR

Mixed Signal Modelling and Verification Engineer: Participating in the verification process for complex mixed signal IC developments and contributing towards improvements in the mixed signal verification methodology. Focus on the verification strategy for complex mixed signal systems, including modelling and selection of appropriate simulation techniques and environments.

Location: Must be based within commutable distance of Edinburgh or Newbury, UK, or willing to relocate prior to beginning employment.

Company

hirify.global solves complex challenges with innovative end-user solutions for the world's top consumer brands and is known for its award-winning culture.

What you will do

• Lead mixed signal verification activities, including resource planning, task assignment, and reporting.
• Define IC verification strategy for complex mixed signal systems, including modelling and selection of appropriate simulation techniques and environments.
• Develop reliable and reusable mixed signal testbenches, compliant with industry standard verification techniques.
• Develop behavioural models using advanced modelling techniques including real number modelling, user-defined types and Verilog AMS.
• Provide tool and methodology support for other Engineers working on mixed signal verification activities.
• Collaborate with other Engineering disciplines to maximize efficiency of development activities.

Requirements

• BEng / BSc / MEng / MSc Degree or equivalent in Electronics/Computer Science or other related discipline.
• Proven track record in delivering 1st time success with complex mixed signal IC’s.
• Experience of mixed signal simulation techniques and tools, including Spectre, AMS and Digital simulation.
• Knowledge of SystemVerilog.
• Experience of analog and digital design.
• Modelling of Analog subsystems using System Verilog and VerilogA/AMS.

Nice to have

• Scripting experience with Python, sh/csh, TCL, Make
• Object orientated programming (OOP) - Use of OOP design patterns
• Knowledge of SVA (SystemVerilog Assertions)
• Metric driven verification - verification planning, requirements extraction - Directed and constrained random verification
• Functional and code coverage analysis

Culture & Benefits

• Personal and professional development opportunities.
• Uniquely flat culture.
• Committed to encouraging an open and collaborative culture where different approaches, ideas, and points of view are respected and valued.