TL;DR

Physical Design Engineer (Semiconductor): Responsible for full chip or block level physical design in advanced technology nodes, focusing on deep floorplanning, clock tree planning, placement, routing, and timing closure. Focus on advanced process nodes, SI/noise closure, ECO tasks, and various validation/qualification tasks like EM/IR, DRC, LVS, and Antenna analysis.

Location: Remote (Ukraine)

Company

%hirify_global% Engineering is a global leader in engineering services, helping innovative companies unleash their potential across various industries.

What you will do

Responsible for all aspects of Physical Design in full chip or block level using advanced technology nodes (10nm and below).
Perform deep floorplanning, partitioning/budgeting, power mesh distribution, clock tree planning and analysis, Scan re-ordering, placement, CTS, place and route.
Cover all relevant activities related to timing analysis (closure through sign-off including SI/noise) and ECO tasks (both functional and timing).
Manage validation/qualification tasks including Formal Verification, EM/IR, DRC, LVS, Antenna, and ERC analysis and fixes.
Contribute to overall Low Power solution development and implementation.
Develop and enhance timing-related scripts for clock skew, critical path, IO interfaces, and constraints partitioning.

Requirements

8+ years desirable experience in RTL2GDSII work on 10nm or below nodes with large designs (500k – 1million+ instances).
Power user of PnR and timing analysis CAD tools from Synopsys and/or Cadence.
Good knowledge of synthesis flow, insertDFT scan/coverage and optimization.
Excellent floorplan, power plan, CTS, place, route, and timing closure skills.
Proficiency using Perl/TCL/Python scripting and Makefile.
Expertise in timing STA/PTSI, signal integrity closure, and ECO generation/implementation.
Excellent EM/IR, DRC, LVS, ERC analysis and fixing skills.
Experience with sign-off tape-out closure work.

Culture & Benefits

Health insurance from the first days of employment.
Christmas holidays from December 25 to December 31.
Cooperation and support for Superhumans center and Veteran HUB.
Internal policy friendly to military and veterans.

Phisical Design Engineer (Semiconductor)