TL;DR

Senior Dft Engineer (Semiconductor): Shaping the quality and reliability of next-generation Wi-Fi ICs by implementing advanced testing strategies and integrating cutting-edge methodologies. Focus on improving test coverage and design for testability, working both independently and collaboratively in a fast-paced environment.

Location: Bristol

Company

%hirify_global% is inspired and supported to develop yourself, valuing and encouraging the continuous development of skills and expertise to the highest levels.

What you will do

Implement and utilize effective and efficient testing strategies.
Integrate BIST into memory designs and validate its functionality.
Insert and validate Embedded Deterministic Test (EDT) and On-Chip Clocking (OCC) methodologies.
Insert and validate scan and iJTAG (Internal JTAG) techniques.
Generate automatic test patterns.
Analyze the test coverage of designs and implement strategies to increase test coverage and the testability.

Requirements

BSc/MSc in Electronics Engineering or similar.
Experience with EDA IC design and verification tools, Digital IC Design and Verification, DFT architecture and implementation, Memory BIST, iJTAG, EDT, OCC, Scan, ATPG and pattern simulations.
Exposure to LEC, VCLP, STA.
Knowledge of scripting languages like Perl, Tcl, Python, or similar.
Experience with Tessent tools, Confluence and JIRA combined with excellent documentation and communication skills.
Ability to work/communicate fluently in English.

Culture & Benefits

Competitive salary with short- and long-term incentive plan.
Flexible working hours.
Medical insurance.
Family-friendly policies, insurances, and benefits.