Platform Integration Lead and Micro Architect (AI)

TL;DR

Platform Integration Lead and Micro Architect (AI): Designing and developing high-performance networks-on-chip for multiple SoCs within hirify.global with an accent on SoC interconnect design, coherent fabrics, and AMBA/PCIe/CXL protocols. Focus on microarchitecture, analyzing power, performance, and area trade-offs, and managing geographically distributed engineering teams.

Location: This role will be eligible for a hybrid work model, splitting time between on-site at an assigned hirify.global site and off-site. Primary locations include US, California, Santa Clara; US, California, Folsom; US, Oregon, Hillsboro; US, Texas, Austin. This position operates on Shift 1 (United States of America).

Salary: $220,920–$311,890 USD

Company

hirify.global invents at the boundaries of technology to make amazing experiences possible for business and society, disrupting industries and solving global challenges.

What you will do

• Lead and manage the integration team within the hirify.global Chassis Group.
• Design and develop high-performance networks-on-chip for multiple SoCs.
• Work with SoC architecture teams to build upon foundation IP components.
• Contribute to SoC interconnect design and microarchitecture.
• Analyze power, performance, and area trade-offs in designs.
• Collaborate with architecture, verification, formal verification, emulation, and firmware teams.

Requirements

• 15+ years of experience in state-of-the-art SOC and/or IP design.
• Deep background in SoC interconnect design and microarchitecture.
• Expertise in coherent and non-coherent fabrics, AMBA/PCIe/CXL protocols, and memory subsystems.
• Strong communication skills and demonstrated ability to work across large, geographically distributed engineering teams across multiple time zones.
• Bachelor's/Master's degree in Science, Electrical Engineering or equivalent.

Nice to have

• 10+ years' experience in microarchitecture and design IP systems, including 5+ years' experience in fabrics for AI SoCs.
• 7+ years of team management experience.
• Expertise in Verilog/System Verilog, Lint/CDC/RDC.
• Experience in designing credit-based interconnect systems with QoS, security, debug/trace, and RAS.
• Deep understanding of coherency concepts.
• Understanding of UAL/UCIe protocols.
• Good understanding of memory subsystems including HBM and LPDDR.

Culture & Benefits

• Eligible for a hybrid work model allowing employees to split time between on-site and off-site work.
• Total compensation package includes competitive pay, stock, and bonuses.
• Benefit programs include health, retirement, and vacation.
• This role is a Position of Trust, requiring consent to and passing an extended Background Investigation.