TL;DR

Senior Design Verification Engineer (Chip Design): Designing and delivering next-generation chassis IPs with an accent on verification strategy, advanced methodologies, and complex protocol validation. Focus on driving first-pass silicon success, owning critical IP blocks, and championing innovation in verification techniques.

Location: On-site in Santa Clara, California, US

Salary: $190,610.00–$269,100.00 USD

Company

%hirify_global% invents at the boundaries of technology to make amazing experiences possible for business and society, driving innovation across various product families.

What you will do

Design, develop, and deliver a comprehensive verification strategy and methodology scaling from IP through subsystems to SoC-level verification.
Design and implement advanced verification environments, tools, and test plans to enable first-pass silicon success.
Collaborate closely with architecture, design, and software teams from product definition through implementation and productization.
Drive ownership of multiple critical blocks and verification components, taking full responsibility for functional signoffs and performance/power metrics.
Lead IP delivery to multiple customers, balancing competing requirements, schedules, and resources.
Champion innovation across simulation, formal, and accelerated verification methodologies, including ML-based flows.

Requirements

BS/MS in Electrical Engineering, Computer Science, or related field, with 12+ years of combined experience.
Extensive background in IP design verification with significant experience in subsystem and SoC-level verification.
Proficiency in interconnects, caches, and memory subsystems, including multiple bus protocols like AMBA (CHI, ACE, AXI), PCIe, UCIe, and CXL, as well as cache coherency.
Experience verifying global functions such as debug, trace, clock & power management, RAS, QoS, and security features.
Expertise in simulation-based verification methodologies including UVM, ABV, and co-simulation, alongside low-power verification techniques and industry-standard EDA tools.
Coding proficiency across System Verilog/UVM, software programming languages (C/C++), and scripting (Python), with a track record of developing reusable verification collateral.

Culture & Benefits

Competitive pay, stock, and bonuses.
Comprehensive benefit programs including health, retirement, and vacation.
Focus on technical excellence and mentorship.
Opportunity to contribute to next-generation technology and disrupt industries.