TL;DR

Silicon Microarchitecture Engineer (AI): Responsible for high-performance machine learning accelerator architecture, micro-architecture, and RTL design with an accent on performance, power, and area trade-offs. Focus on system architecture definition and evaluation, chip design collaboration, and tool development guidance.

Location: London, UK

Company

%hirify_global% is a team of scientists, engineers, and machine learning experts advancing AI for widespread public benefit and scientific discovery.

What you will do

Participate in a fast-paced interdisciplinary team of experts from Machine Learning, Hardware, Programming Languages, and Systems.
Design high-performance machine learning accelerator architecture, micro-architecture, and RTL.
Select and integrate in-house and third-party IP.
Explore trade-offs of future architecture designs in terms of performance, power, energy, and area.
Participate in the system architecture definition and evaluation.
Collaborate with simulation and PD teams to maintain up-to-date cost functions for architecture evaluation.

Requirements

Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
7+ years of experience in RTL design in Verilog/System Verilog.
5+ years of experience in micro-architecture definition.
3+ years of experience in RTL design verification.
Experience with high-performance compute IPs (e.g., GPUs, DSPs, or machine learning accelerators).
Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis.

Nice to have

Working experience developing with C++ & Python.
Physical Design background or hands-on experience.
Design Verification background or hands-on experience.
Knowledge/understanding of high-level synthesis.
Working knowledge of transformer-based large language models.

Culture & Benefits

Value diversity of experience, knowledge, backgrounds, and perspectives.
Committed to equal employment opportunity.