TL;DR

RF Analog Layout Engineer (FinFET): Designing and optimizing layouts for high-frequency analog/RF blocks in FinFET technology with an accent on parasitic and matching constraints, shielding, and EM/IR reliability. Focus on optimizing routing for high-frequency signals, ensuring compliance with advanced design rules, and collaborating with RF designers.

Location: Onsite in Ampelokipoi, Athens, or Thessaloniki, Greece

Company

%hirify_global% is a global leader in consulting, technology services, and digital transformation.

What you will do

Design layouts for RF circuits such as LNAs, mixers, VCOs, and PLL sub-blocks in FinFET technology.
Optimize routing for high-frequency signals, minimizing parasitic capacitance and inductance.
Implement shielding strategies (coaxial, differential, ground shields) to reduce coupling and crosstalk.
Address EM/IR reliability for high-current RF paths and ensure compliance with advanced DRC/LVS rules.
Apply matching techniques for RF differential pairs and passive components (inductors, capacitors).
Collaborate with RF designers to meet performance targets for gain, noise figure, and phase noise.

Requirements

Hands-on experience in RF layout design at FinFET nodes.
Deep understanding of parasitic control for high-frequency circuits.
Familiarity with EM modeling, substrate coupling, and isolation techniques.
Proficiency in RF-aware EDA tools and post-layout simulation flows.
Knowledge of reliability and aging effects in RF devices and mitigation strategies.
English: B2 required.

Nice to have

Experience with RF sign-off flows and EM extraction tools.
Ability to optimize layout for low phase noise and high linearity.
Scripting skills for RF layout automation and verification.

Culture & Benefits

Permanent contract.