TL;DR

Senior Design Engineer (AI): Developing logic design, RTL coding, and simulation for AI SoC designs, integrating IP blocks and subsystems with an accent on defining architecture, microarchitecture features, and quality checks. Focus on optimizing logic for power, performance, area, and timing goals while collaborating with verification teams and ensuring design integrity.

Location: This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned %hirify_global% site and off-site. Primary locations are Folsom, Santa Clara, California, and Hillsboro, Oregon, USA.

Salary: $190,610.00-269,100.00 USD (Annual)

Company

%hirify_global%'s AI SoC organization develops cutting-edge products powering a wide range of AI applications, from edge devices to data center accelerators.

What you will do

Develop logic design, register transfer level (RTL) coding, and simulation for SoC designs.
Integrate IP blocks and subsystems into full chip SoC or discrete component designs.
Participate in defining architecture and microarchitecture features of the blocks being designed.
Perform quality checks across various logic design aspects and optimize logic for power, performance, area, and timing goals.
Collaborate closely with verification teams, review verification plans, and resolve failing RTL tests.
Drive silicon bring-up and post-silicon validation, including debug and performance analysis.

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science.
7+ years of experience in RTL design and implementation for ASIC/SoC development.
Proven ability to solve complex design challenges such as clock domain crossings, power optimization, and timing closure.
Hands-on experience with SoC system integration and multicore CPU subsystem design.
Strong knowledge of standard bus protocols (AXI, AHB) and embedded processor architectures.
Proficiency in scripting (Python, TCL) for automation and design flow optimization and familiarity with industry standard EDA tools.
Work from one of the assigned %hirify_global% sites in Folsom, Santa Clara (California) or Hillsboro (Oregon), USA.

Culture & Benefits

Total compensation package that ranks among the best in the industry, including competitive pay, stock, and bonuses.
Benefit programs which include health, retirement, and vacation.
Opportunity to shape the future of AI hardware in a fast-paced environment.
Strong communication skills, collaborative mindset, and leadership opportunities.
Passion for innovation, continuous learning, and tackling technical challenges.