TL;DR

Low Latency C++ Developer (Algo Trading): Building ultra-low latency trading systems and a real-time trading rules engine using a hybrid of FPGA hardware and high-performance C++ with an accent on deterministic execution and rapid market interaction. Focus on designing cycle-accurate FPGA, implementing lock-free data structures, and optimizing system performance for real-time orchestration.

Location: Onsite in Shanghai, Mainland China

Company

%hirify_global% is a leading global wealth manager and universal bank providing diversified asset management solutions and investment banking capabilities.

What you will do

Design and implement real-time trading rules and risk checks using FPGA (Verilog/VHDL) and C++.
Architect cycle-accurate FPGA designs and high-speed network interfaces.
Build simulation and verification frameworks for FPGA reliability.
Interface C++ applications with FPGA hardware for real-time orchestration.
Implement lock-free data structures and concurrency control in Linux.
Analyze system performance and resolve latency bottlenecks.

Requirements

7+ years in FPGA (Verilog/VHDL) and low-latency C++ development.
Expert in C++17/20/23, Linux system programming, and concurrency.
Deep knowledge of FPGA toolchains (Vivado, Quartus) and timing closure.
Experience with high-speed networking and hardware acceleration.
Strong background in shared memory IPC and lock-free systems.
Degree in Computer Science, Electrical Engineering, or related field.

Nice to have

Familiarity with market microstructure and trading protocols (FIX, ITCH).

Culture & Benefits

Join a high-performance team building ultra-low latency trading systems.
Collaborate with global IT, Quants, and Traders across asset classes.
Opportunities through the career returners program.
Access to new challenges and a supportive team.
Enjoy a flexible and inclusive culture with diverse skills, experiences, and backgrounds.