Algo Trading Low Latency C++ Developer (Fintech)

TL;DR

Algo Trading Low Latency C++ Developer (Fintech): Designing and implementing a trading rules engine for real-time controls using a hybrid of FPGA hardware and high-performance C++ with an accent on deterministic execution and rapid interaction with the markets. Focus on cycle-accurate FPGA designs, high-speed network interfaces, and low-latency network apps using kernel bypass.

Location: Onsite in Shanghai, China

Company

hirify.global is a leading and truly global wealth manager and the leading universal bank in Switzerland.

What you will do

• Design and implement real-time trading rules and risk checks using FPGA (Verilog/VHDL) and C++.
• Architect cycle-accurate FPGA designs and high-speed network interfaces (10/25/40/100GbE, RoCEv2).
• Build low-latency network apps using kernel bypass (e.g., Rivermax).
• Analyze system performance and resolve latency bottlenecks.
• Collaborate with global IT, Quants, and Traders across asset classes.
• Provide Level 3 support for production systems.

Requirements

• 7+ years in FPGA (Verilog/VHDL) and low-latency C++ development.
• Expert in C++17/20/23, Linux system programming, concurrency.
• Deep knowledge of FPGA toolchains (Vivado, Quartus), timing closure.
• Experience with high-speed networking and hardware acceleration.
• Strong background in shared memory IPC and lock-free systems.
• Degree in Computer Science, Electrical Engineering, or related field.

Nice to have

• Familiarity with market microstructure and trading protocols (FIX, ITCH) is a plus.

Culture & Benefits

• Collaboration is at the heart of everything we do.
• Opportunities to grow and flexible working options when possible.
• Inclusive culture brings out the best in our employees.