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2 дня назад

Digital Signal Processing Engineer

120 000 - 192 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
middle/senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR

Digital Signal Processing Engineer (SerDes/PAM4): Designing digital signal processing blocks for next-generation optical data center connectivity products with an accent on performance, power, and cost optimization. Focus on translating CDR and equalization architectures into Verilog code for logic synthesis, ensuring high-speed data center networking.

Location: Must be located in San Jose, California

Salary: $120,000 - $192,000

Company

hirify.global is a global technology leader that designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions.

What you will do

  • Design digital signal processing blocks for optical data center connectivity products.
  • Translate CDR and equalization architectures into Verilog code for logic synthesis.
  • Utilize Matlab, Simulink, and Verilog-HDL/System Verilog for coding and simulations.
  • Work with front-end tools such as NCVerilog, NCSIM, Simvision, and Spyglass.
  • Contribute to design for test (DFT) and implement DFT-friendly RTL.

Requirements

  • MS in Electrical Engineering or Computer Engineering with 6+ years or PhD with 3+ years of experience in digital signal processing design for SerDes and serial link high-speed data center networking.
  • Deep understanding of DSP-based optical and electrical interconnect architectures such as 100G/200G/400G per lane PAM4 and NRZ design trade-offs.
  • Experience translating CDR and equalization architectures into Verilog code for logic synthesis.
  • Proficient with Matlab, Simulink and Verilog-HDL/System Verilog coding.
  • Experience with front-end tools such as NCVerilog, NCSIM, Simvision, Spyglass.
  • Experience in synthesis, CDC, static timing analysis.

Nice to have

  • Good understanding of high-speed DSP applications and algorithms.
  • Prior experience with high-speed ADC, FFE, DFE, CDR Adaptation algorithms for PAM4 signals.
  • Deep understanding of Signal Integrity and Power Integrity modeling for High-Speed designs.
  • Strong written and verbal communication skills.
  • Proactive, collaborative, and creative approach to innovation.

Culture & Benefits

  • Competitive and comprehensive benefits package: Medical, dental, and vision plans.
  • 401(K) participation including company matching.
  • Employee Stock Purchase Program (ESPP).
  • Employee Assistance Program (EAP).
  • Company paid holidays, paid sick leave and vacation time.

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