TL;DR

Senior Design Engineer (AI/SoC): Defining, implementing, and validating complex SoC IP blocks and subsystems for AI applications with an accent on power, performance, and security requirements. Focus on architectural trade-offs, RTL development, and comprehensive verification of silicon for next-generation AI solutions.

Location: Hybrid (US, California, Folsom)

Salary: $214,730.00-303,140.00 USD

Company

%hirify_global%’s AI SoC organization develops cutting-edge products powering a wide range of AI applications—from edge devices to data center accelerators.

What you will do

Evaluate architectural trade-offs across features, performance, power, and system limitations.
Define microarchitecture and implement RTL in Verilog/SystemVerilog for complex SoC IP blocks.
Collaborate with verification teams to ensure comprehensive coverage and robust validation.
Develop and maintain timing constraints, guiding physical design teams.
Drive post-silicon validation, debug, and performance analysis.
Mentor junior engineers and contribute to design methodology and quality.

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science with 10+ years of experience.
7+ years of experience in RTL design and implementation for ASIC/SoC development.
Proven ability to solve complex design challenges such as clock domain crossings, power optimization, and timing closure.
Hands-on experience with SoC system integration and multicore CPU subsystem design.
Strong knowledge of standard bus protocols (AXI, AHB) and embedded processor architectures.
Proficiency in scripting (Python, TCL) for automation and design flow optimization.

Culture & Benefits

Total compensation package includes competitive pay, stock, bonuses, health, retirement, and vacation.
Eligible for a hybrid work model, splitting time between on-site and off-site work.
Commitment to diversity, inclusion, education, and sustainability.