TL;DR

High Speed SerDes Logic Design PEY Undergrad Intern (SerDes): Designing and optimizing cutting-edge high-speed SerDes solutions for %hirify_global% products with an accent on RTL coding, analog circuit modeling, and ML-based optimization. Focus on gaining hands-on experience in digital design, analog circuit modeling, and developing innovative methodologies.

Location: Hybrid work model in Canada, Toronto.

Company

%hirify_global% makes possible the most amazing experiences of the future, inventing at the boundaries of technology to create value for stockholders, customers, and society.

What you will do

Perform logic design and RTL coding for high-speed SerDes.
Conduct RTL simulation and verification.
Develop behavioral models for analog circuits.
Research and implement modeling optimization techniques using Machine Learning.
Develop scripts and design flows to improve efficiency.
Provide support for SoC integration.

Requirements

Must be pursuing a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, Engineering Science (Electrical and Computer), or Engineering Science (Machine %hirify_global%ligence) or a related field.
This position is not eligible for %hirify_global% Immigration Sponsorship.
English: B2 required.

Nice to have

Fundamental knowledge of electronics and digital hardware concepts.
Basic understanding of digital design practices, including RTL coding in Verilog and running/debugging simulations.
Familiarity with ASIC design flows for deep sub-micron technologies.
Strong scripting and/or software development skills.
Background in AI/ML is an asset.

Culture & Benefits

Eligible for a hybrid work model, splitting time between on-site at %hirify_global%'s Toronto location and off-site.
Work in a team that values problem-solving, resilience under pressure, and self-motivation.
Join a team that values teamwork and shared success.
Committed to a culture of accessibility and provides accommodations to applicants and employees with disabilities.