Design Engineer (AI SoC)

TL;DR

Design Engineer (AI SoC): Developing logic design, RTL coding, and simulation for AI SoC designs, integrating IP blocks and subsystems. Focus on defining architecture and microarchitecture features, optimizing logic for power, performance, and timing, and ensuring design integrity for physical implementation.

Location: This role will be eligible for our hybrid work model in Folsom, California, United States or Santa Clara, California, United States, allowing employees to split their time between working on-site at their assigned hirify.global site and off-site. Only candidates authorized to work in the US will be considered.

Salary: $139,710.00–$197,230.00 USD (annual)

Company

hirify.global invents at the boundaries of technology to make amazing experiences possible for business and society, developing cutting-edge products powering a wide range of AI applications.

What you will do

• Develop logic design, register transfer level (RTL) coding, and simulation for SoC designs.
• Integrate IP blocks and subsystems into full chip SoC or discrete component designs.
• Participate in defining architecture and microarchitecture features of the blocks being designed.
• Perform quality checks across various logic design aspects, ranging from RTL to timing/power convergence.
• Work closely with verification teams to achieve full coverage and robust validation.
• Support silicon bring-up and post-silicon validation activities, including debug and performance analysis.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science.
• 4+ years of experience in RTL design and implementation for ASIC/SoC development.
• Proficiency in Verilog/SystemVerilog for RTL coding and design.
• Experience with synthesis tools and timing closure methodologies.
• Work authorization for the United States is required.

Nice to have

• Understanding of clock domain crossings, power optimization, and timing closure.
• Exposure to SoC system integration and CPU subsystem design.
• Familiarity with standard bus protocols (AXI, AHB) and embedded processor architectures.
• Knowledge of high-speed and low-power design techniques.
• Experience with static timing analysis (STA) and formal verification tools.
• Basic scripting skills (Python, TCL) for automation.

Culture & Benefits

• Competitive pay, stock, bonuses, as well as benefit programs which include health, retirement, and vacation.
• Hybrid work model allowing employees to split their time between working on-site and off-site.
• Opportunity to work in a dynamic environment with abundant learning opportunities.
• Commitment to diversity, inclusion, education, and sustainability.