TL;DR

Senior Analog Layout Engineer (FinFET): Designing and implementing analog layouts for advanced FinFET nodes, ensuring compliance with design rules and optimizing for performance, reliability, and manufacturability. Focus on parasitic effects mitigation, matching techniques, and collaboration with circuit designers for layout optimization and yield.

Location: Onsite in Belgrade, Nis, or Novi Sad, Serbia

Company

%hirify_global% is a global leader in consulting, technology services, and digital transformation.

What you will do

Develop analog layouts for circuits such as amplifiers, references, bias blocks, and data converters in FinFET nodes.
Apply best practices for DRC/LVS closure, including advanced tips and tricks for efficient debugging.
Perform EM/IR analysis and implement layout changes to meet reliability targets.
Address parasitic effects through careful routing, shielding, and post-extraction corrections.
Implement matching techniques (common-centroid, interdigitation, dummy devices) for precision circuits.
Collaborate with circuit designers to optimize layout for performance and yield.

Requirements

Proven experience in FinFET layout design for analog IP.
Strong knowledge of LDE effects (WPE, STI, LOD) and mitigation strategies.
Proficiency in industry-standard EDA tools (Cadence Virtuoso, Calibre, PVS).
Familiarity with parasitic extraction flows and correlation techniques.
Understanding of reliability mechanisms (BTI, HCI) and guard-banding in layout.

Nice to have

Experience with advanced-node design rules and color-aware layout.
Knowledge of EM/IR verification methodologies and sign-off flows.
Ability to automate layout tasks using SKILL or Python scripts.