Standard Cell Library Design Engineer

TL;DR

Standard Cell Library Design Engineer (Embedded_IoT_Dev): Design, develop, and deliver standard cell library foundation IP with an accent on generating and verifying library EDA models, running regression and quality checks, and process automation. Focus on digital and mixed-signal circuit design, FinFet and RibbonFet/GAA process nodes, and scripting for automation.

Location: Singapore-Yishun, Singapore. Singapore Citizen/PR only

Company

hirify.global is a global technology leader designing, developing, and supplying semiconductor and infrastructure software solutions.

What you will do

• Generate and verify library EDA models.
• Run regression and quality checks on library deliverables.
• Interface with design teams to support their requirements.
• Implement process automation using scripting for consistent and faster throughput.

Requirements

• Must be Singapore Citizen or PR.
• Knowledge of digital or mixed-signal circuit design.
• Understanding of cell layout or physical design.
• Familiarity with FinFet, RibbonFet/GAA process nodes.
• Experience with verilog, lef, liberty, and other industry standard EDA models.
• Experience with EDA tools used in STA and PnR.
• Strong scripting skills in Unix, Perl, TCL, or Python.

Nice to have

• Experience with .lib syntax including NLDM/CCS/LVF.
• Experience with Virtuoso and Cadence Skill programming.

Culture & Benefits

• Equal opportunity employer.
• Collaborative work environment across teams.