TL;DR

Design Engineer - Chip Floorplanner (ASIC): Defining and optimizing chip-level physical architecture and integration for advanced ASICs in deep sub-micron technologies with an accent on die layout, hierarchy, and placement of major functional blocks. Focus on balancing performance, power, and area (PPA) targets and driving top-level timing closure and congestion analysis.

Location: Onsite in Fort Collins, Colorado, USA

Salary: $127,100–$203,400 annually (base)

Company

%hirify_global% is a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions.

What you will do

Define and optimize top-level floorplan architecture, including die size estimation and partitioning.
Drive macro placement, power grid design, clock distribution planning, and pin placement.
Collaborate closely with RTL, timing, and packaging teams to balance performance, power, and area (PPA) targets.
Lead top-level timing closure, congestion analysis, and ECO implementation to ensure tapeout readiness.
Coordinate with block owners and integration teams for smooth block-level to top-level convergence.
Support cross-functional design integration and apply a deep understanding of PnR, timing closure, physical verification, and IR/EM analysis.

Requirements

Education: BS in Electrical or Computer Engineering with 12+ years of relevant experience, or MS with 10+ years of relevant experience.
Strong foundation in VLSI design principles and ASIC physical design fundamentals.
In-depth experience with floorplanning, die partitioning, and hierarchical design.
Working knowledge of PLLs, clock networks, power delivery, and timing-critical structures.
Familiarity with physical verification, DRC/LVS, and congestion/power analysis.
Strong experience with TCL scripting and Linux environments.

Nice to have

Proficiency in Python, Perl, or Ruby.
Experience with Cadence or equivalent physical design tools.

Culture & Benefits

Competitive and comprehensive benefits package including Medical, dental, vision plans.
401(K) participation with company matching and Employee Stock Purchase Program (ESPP).
Employee Assistance Program (EAP), company paid holidays, paid sick leave, and vacation time.
Opportunity to work on high-performance SoC designs for cutting-edge AI, Cellular, Networking, Computing, and Storage products.
Join a world-class engineering group developing custom CMOS ASICs.
Work on advanced 3 nm and smaller process nodes.