TL;DR

Design Engineer (ASIC): Contributing to the physical implementation of large-scale ASICs for AI, Cellular, Networking, Computing, and Storage products with an accent on floorplanning, placement, clock tree synthesis, routing, and timing closure. Focus on optimizing high-performance SoC designs for 5nm and smaller process nodes and ensuring physical verification and signoff.

Location: Onsite in Fort Collins, Colorado, USA

Salary: $60,200 – $96,300 annually

Company

%hirify_global% is a global technology leader that designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions.

What you will do

Contribute to the physical design implementation of large-scale ASICs (multi-hundred-million gate complexity).
Support key design activities including floorplanning, placement, clock tree synthesis, routing, timing closure, and physical verification (DRC/LVS).
Collaborate with cross-functional teams on block-level integration, timing analysis, and design signoff.
Utilize both commercial and in-house EDA tools for design, implementation, and verification.
Contribute to design flow improvements, automation, and deep sub-micron methodology development.
Assist in timing analysis, power planning, IR/EM checks, and post-route optimization, gaining exposure to the complete ASIC design cycle.

Requirements

Solid understanding of VLSI design, CMOS logic, and digital circuit fundamentals.
Familiarity with ASIC physical design concepts such as placement, routing, and timing.
Strong analytical and debugging skills, with the ability to quickly learn new tools and flows.
Proficiency in UNIX/Linux environments.
Working knowledge of TCL.
Bachelor’s or Master’s degree in Electrical or Electronics Engineering.

Nice to have

Familiarity with Python or Perl.
Exposure to EDA tools such as Cadence Innovus, Synopsys ICC2, or PrimeTime.

Culture & Benefits

Competitive and comprehensive benefits package including medical, dental, and vision plans.
401(K) participation including company matching and Employee Stock Purchase Program (ESPP).
Company paid holidays, paid sick leave, and vacation time.
Opportunity to work in a fast-paced R&D environment within a world-class engineering group.
%hirify_global% is an equal opportunity employer.