Front-End Design Engineer (RTL & Timing)

TL;DR

Front-End Design Engineer (AI): Owning the front-to-back implementation of complex IP, from micro-architecture and RTL in SystemVerilog through synthesis, CTS, and P&R, with an accent on driving power/timing quality and leveraging AI/agent tooling for automation. Focus on developing innovative high-speed interconnect IP for AI and High Performance Computing applications, integrating LLM/agents for flow automation and quality tracking.

Location: Onsite in Toronto, Canada

Company

hirify.global enables critical data communication, developing industry-leading high-speed interconnect IP for data centers, AI, and autonomous vehicles.

What you will do

• Own front-to-back IP implementation from micro-architecture & RTL in SystemVerilog to synthesis, CTS, and P&R handoff.
• Perform synthesis and QoR analysis, guiding retiming, pipeline/boundary placement, logic restructuring, and RTL optimizations for PPA.
• Author and maintain SDC for timing constraints, perform timing reviews, and partner with STA/PD to close MCMM corners.
• Define clock architecture, CTS targets, and boundary timing to achieve robust clock closure.
• Conduct power analysis and drive micro-architectural improvements and clock/power-gating.
• Integrate LLM/agents to auto-triage logs & violations, lint constraints, detect regressions, and recommend fixes.
• Collaborate on design quality sign-off (lint/CDC/RDC, FM/LEC) and support DFT/test-mode constraints.
• Work cross-functionally with RTL, PD, STA, DV, and DFT teams, and mentor peers on front-to-back design thinking.

Requirements

• Bachelor/Master in Computer/Electrical Engineering and substantial experience delivering silicon from RTL through PnR.
• SystemVerilog RTL expertise with strong micro-architecture instincts for PPA and simulation debug.
• Proficiency in Synthesis & STA, with hands-on experience using tools like Design Compiler, Fusion, or PrimeTime.
• SDC mastery, including clocks, generated clocks, clock groups, exceptions, and hierarchical constraints for MCMM sign-off.
• Practical understanding of CTS/P&R awareness, including ICC2 flows, useful skew, and boundary timing effects.
• Experience with Power analysis workflows (SAIF/VCD, PrimeTime PX, vector- vs vectorless-based power, power-driven RTL/synthesis techniques).
• Strong Tcl & Python skills for constraint generation/validation, report mining, dashboards, and CI.
• Curiosity and enthusiasm for applying LLMs/agents to design flow automation.

Nice to have

• Familiarity with UPF/low-power implementation, IR/EM-aware considerations, and LVF/variation.
• Experience with high-speed/mixed-signal interfaces (DDR, PCIe, SerDes) and digital/analog boundary timing.

Culture & Benefits

• Flexible work environment to support employee well-being.
• Comprehensive benefits package, including Restricted Stock Units (RSUs), short-term incentive program, and Employee Stock Purchase Plan (ESPP).
• Health & Wellness programs, comprehensive health plans, Wellness Spending Account (WSA), and Employee Assistance Program (EAP).
• Flexible time off options, including paid vacation, paid holidays, and parental leave.