TL;DR

Engineer I-Verification (FPGA): Verifying RISC-V based System on a Chip (SOC) semiconductor products integrated into state of art FPGA architectures with an accent on leading-edge verification tools and methodologies. Focus on silicon design and logic design, performing simulations and debugging verification testbenches.

Location: San Jose, CA

Salary: $68,640 - $128,000

Company

%hirify_global% designs the technology that runs the world and is committed to employee development, values-based decision making, and a strong sense of community.

What you will do

Write verification specifications, plans, and documentation.
Develop test benches and automate regression plans using System Verilog and 'C' in a UVM environment.
Develop make files, Python, and Perl scripts to automate verification tasks.
Perform block-level verification and contribute to SOC chip-level verification.
Manage verifications, simulations, and debugging of verification testbenches.
Interface with cross-functional teams to understand use cases and collaborate on SOC verification activities.

Requirements

Bachelors or Masters in Electrical Engineering with 0-3 years' relevant research or work experience.
Adaptability and flexibility in fast-paced environments.
Excellent verbal and written communication skills.
Proactive problem-solving attitude and a willingness to take initiative.

Culture & Benefits

Competitive base pay, restricted stock units, and quarterly bonus payments.
Health benefits start on day one.
Retirement savings plans.
Industry-leading ESPP program with a 2-year look-back feature.