Senior Technical Staff Engineer - Architect (Memory Interconnect)

TL;DR

Senior Technical Staff Engineer - Architect (Memory Interconnect): Leading cross-functional teams to deliver high-performance IP integrations into FPGA products with an accent on meeting market and customer requirements across a broad range of use cases and application spaces. Focus on architecture and implementation for Analog, ASIC & FPGA design development, integration, and deployment for high-performance parallel interconnect.

Location: San Jose, CA

Salary: $88,000 - $232,000

Company

hirify.global Inc. designs the technology that runs the world.

What you will do

• Lead cross-functional teams to deliver high-performance IP integrations into Microchip FPGA products.
• Work on architecture & implementation for Analog, ASIC & FPGA design development, integration, and deployment for high-performance parallel interconnect.
• Understand customer use cases and the role of IP in overall system architecture.
• Work cross-functionally with other architects, designers, and back-end implementation teams.
• Lead and manage other engineers in the team.

Requirements

• MSc or higher in EE, CS, CE or other applicable disciplines
• 12+ years of industrial experience
• Proven experience in ASIC & FPGA IP development, integration, and deployment, including all stages of development from Synthesis, constraint management, place & route, floorplanning, timing closure, CDC/RDC
• Knowledge and experience with Synopsys & Cadence ASIC flows

Nice to have

• Knowledge and experience with system-level performance modeling in TLM/SystemC/Other.
• Scripting for EDA in Perl, Python, Tcl
• Experience in technical leadership and people management

Culture & Benefits

• Competitive base pay, restricted stock units, and quarterly bonus payments.
• Health benefits that begin day one, retirement savings plans, and an industry-leading ESPP program.
• Commitment to employee development, values-based decision making, and strong sense of community.