TL;DR

Experienced Full Chip Timing Designer: Performing timing analysis and optimization for SoCs with an accent on developing methodologies for high-quality timing models. Focus on collaborating with various design teams to ensure efficient chip integration and timing closure.

Location: On-site in Petah-Tikva, Israel

Company

%hirify_global% is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs.

What you will do

Build and maintain automation environments for timing model generation
Support backend platforms to resolve timing violations
Drive timing closure across physical design stages
Innovate with AI-based tools, indicators, and ad-hoc automation
Own constraint management and budgeting flows using top high-end CAD tools

Requirements

BSC Electronics Engineering or a related field
5+ years of experience in scripting and software development (TCL, Python, AI-based coding tools)
Deep knowledge of backend design: synthesis, place & route (P&R), STA (Primetime preferred)
Hands-on experience with optimization flows of STA tools
Proactive, self-driven mindset with strong ownership attitude
Customer-focused and collaborative team player
Curious, innovative, and eager to push boundaries