Вакансия из Hirify Global, списка международных tech-компаний Для мэтча и отклика нужен Plus
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Роль описана чётко и предполагает техническое лидерство в крупной EDA-компании, но требование 20+ лет опыта делает круг подходящих специалистов очень узким.
Экстремальный порог
Актуальные технологии
Зона ответственности ясна
Мэтч & Сопровод
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Описание вакансии
Текст:
Hirify AI/Оригинал
TL;DR
EDA Architect Engineer – Debug, Analysis & FPGA Prototyping (EDA/RTL/C++): Architecting frontend EDA tools for RTL and gate-level debug, waveform analysis, design visualization, and FPGA-based prototyping with an accent on performance, scalability, and large-scale SoC design support. Focus on solving complex customer design issues, improving interactive analysis flows, and translating semiconductor customer requirements into production-ready technical solutions.
Location: Hsinchu, Taiwan
Company
hirify.global develops technology and electronic design automation solutions for semiconductor and system companies.
What you will do
Architect and enhance frontend EDA tools for RTL and gate-level debug, waveform analysis, and design visualization.
Improve performance, capacity, usability, and developer productivity for large-scale SoC designs.
Establish baseline performance metrics for interactive editing, debugging, and analysis flows.
Investigate and resolve complex customer issues involving RTL, netlists, timing, and simulation data.
Own frontend initiatives from concept through deployment and translate customer requirements into technical roadmaps.
Mentor senior and junior engineers across global development teams and collaborate with semiconductor and system customers.
Requirements
MS in Computer Science, Electrical Engineering, or equivalent practical experience.
20+ years of experience in EDA tool development, with strong emphasis on frontend debug and analysis.
Deep understanding of RTL, netlist, simulation, and verification flows.
Experience improving tool performance, scalability, and developer productivity.
Strong software engineering skills in C/C++, data structures, performance profiling, and large-codebase development.
Experience working directly with customers on complex design and tool-flow challenges.
Nice to have
Hands-on experience with frontend design debug platforms.
Background in FPGA-based prototyping or emulation systems for SoC validation.
Experience leading cross-site or multidisciplinary engineering teams.
Track record of delivering order-of-magnitude improvements in performance or productivity.
Patents or publications related to EDA, debug, or design productivity.
Culture & Benefits
Full-time position based in Hsinchu, Taiwan.
Work involves collaboration with global development teams and leading semiconductor and system customers.
Focus on impactful technology work solving complex engineering problems.
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