Senior Staff Engineer, Physical Design

Location: Singapore

Company

hirify.global develops semiconductor solutions and next-generation processors and ASICs for enterprise, cloud, AI infrastructure, data centers, and networking.

What you will do

• Drive RTL-to-GDS implementation, including synthesis, place and route, timing analysis, and timing closure.
• Perform timing and logic ECOs to achieve power, performance, and area targets.
• Debug timing, congestion, and implementation issues in complex designs.
• Develop physical design methodologies, automation, and flows using Tcl, Perl, and Python.
• Collaborate with RTL, architecture, timing, and CAD teams to deliver silicon products.

Requirements

• Bachelor's degree with 6–8 years of relevant experience, or a Master's/PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Understanding of RTL-to-GDS physical design flow and digital design fundamentals.
• Experience with synthesis, place and route, and static timing analysis.
• Proficiency in Tcl, Perl, and Python scripting and software development fundamentals.
• Knowledge of Verilog and/or VHDL.
• Strong analytical, problem-solving, and communication skills.
• Resilience and adaptability when solving complex technical challenges.
• Ownership, accountability, and commitment to engineering excellence.

Culture & Benefits

• Full-time role within a collaborative, transparent, and inclusive work environment.
• Eligible for bonus and equity plans, including a new-hire equity grant and annual equity refreshers.
• Competitive compensation and benefits, with tools and resources for professional growth and development.
• AI tools, transcription apps, automated note-taking bots, and real-time answer generators are not permitted during interviews; unauthorized use results in disqualification.
• Access to export-controlled technology or software may require eligibility under U.S. export control laws and an export license review before employment.