Senior Compiler Performance Engineer (AI/HPC)

Location: On-site in PRC, Shanghai, China.

Company

Compiler Engineering develops software technologies for heterogeneous computing across Intel CPU and GPU platforms, supporting AI, HPC, and other demanding workloads.

What you will do

• Lead performance analysis of real-world applications, AI/HPC workloads, and industry benchmarks across compiler, runtime, library, and microarchitecture layers.
• Design and productize compiler optimizations and code generation features for Intel CPUs and GPUs, from prototypes through shipping quality.
• Own performance targets for a compiler component or workload domain and track regressions and gains through continuous integration.
• Advance heterogeneous and offload compilation across SYCL, OpenMP, Triton, MLIR, and DSL paths.
• Collaborate with hardware architecture teams, influence technical direction, review designs and code, and contribute to upstream open-source communities.
• Mentor junior engineers and represent the team's work to partners, customers, and the broader ecosystem.

Requirements

• Master's or PhD in Computer Science, Computer Engineering, or a related field with 5+ years of relevant industry experience, or a Bachelor's degree with 8+ years.
• Strong knowledge and hands-on experience in modern C++, data structures and algorithms, and compiler theory.
• Production experience in at least one compiler-stack area: middle-end optimization, backend code generation, language front end, or runtime and offload support.
• Demonstrated experience analyzing and tuning performance of real-world applications on CPU and/or GPU.
• Proven ability to analyze and solve complex technical problems and deliver features through a full product cycle.
• Excellent written and oral communication skills, including the ability to explain technical details to engineers, architects, and stakeholders.

Nice to have

• Substantial experience with LLVM compiler infrastructure, including upstream contributions; MLIR experience is a strong plus.
• Deep knowledge of Intel x86 instruction set architecture and Advanced Vector Extensions, or GPU architecture and execution models.
• Experience with heterogeneous and parallel programming models such as SYCL, OpenMP offload, Triton, OpenCL, or CUDA.
• Experience optimizing AI/ML workloads or integrating compiler technology with PyTorch and inference engines.
• Experience with CI and performance-tracking infrastructure at scale.
• Experience leading projects across geographies and mentoring engineers.

Culture & Benefits

• On-site work model in Shanghai, China.
• Collaboration with hardware architecture teams and open-source communities.
• Opportunities to shape compiler and software-tool vision across CPU, GPU, and accelerator platforms.
• Employment is subject to ethical hiring practices; no recruitment, medical examination, or other hiring fees are charged.