SoC Engineer (AI Accelerators)

Location: San Francisco, United States; hybrid

Salary: $287K–$485K base pay annually, plus equity and eligible performance-related bonuses

Company

OpenAI is an AI research and deployment company developing products and systems intended to ensure that general-purpose artificial intelligence benefits humanity.

What you will do

• Architect, design, and integrate first-party AI accelerator SoCs, including processors, interconnects, I/O, and platform infrastructure.
• Define SoC architectures and implement microarchitecture and RTL for embedded processors, AMBA fabrics, peripheral subsystems, PCIe, Ethernet, and die-to-die interfaces.
• Integrate Arm Cortex-M and Cortex-A processors, AXI/APB fabrics, third-party controller IP, controller and PHY interfaces, and related glue logic.
• Define reset, boot, configuration, initialization, recovery, power-management, debug, test, and security behavior with firmware and software teams.
• Coordinate with third-party IP vendors on requirements, capability evaluation, deliverables, integration, and issue resolution.
• Carry designs through pre-silicon validation, silicon bring-up, and post-silicon debug while collaborating across architecture, design, verification, physical design, and software.

Requirements

• Experience in SoC architecture, RTL design, and subsystem or full-chip integration, with hands-on ownership through implementation and silicon bring-up.
• Familiarity with Arm Cortex-M and Cortex-A processor subsystems and AMBA protocols and interconnects including AXI and APB.
• Understanding of PCIe protocols and experience configuring, integrating, and debugging controller IP.
• Experience integrating high-speed I/O, including SerDes/PHY interfaces and die-to-die links.
• Experience working directly with third-party IP vendors to evaluate technical fit, communicate requirements, and resolve integration and debugging issues.
• Understanding of reset and boot architecture and hardware, firmware, and software interactions during initialization and recovery.
• Experience designing for debug, test, and security and assessing how these requirements affect the broader system.
• Ability to write and debug Verilog/SystemVerilog and build scripts or tools that improve integration efficiency and reliability.

Nice to have

• Experience creatively applying automation and AI tools to hardware design and integration work.
• Interest in working across multiple domains and taking broad ownership on a small, dynamic team.

Culture & Benefits

• Small, dynamic hardware team with evolving priorities, technical breadth, hands-on engineering, and broad ownership.
• Hybrid work in San Francisco with daily office meals and eligible meal delivery credits.
• Medical, dental, and vision insurance, employer HSA contributions, FSA options, and a 401(k) plan with employer match.
• Paid parental, medical, caregiver, sick, and safe leave; paid holidays; paid office closures; and flexible PTO for exempt employees.
• Mental health and wellness support, employer-paid life and disability coverage, and an annual learning and development stipend.
• Relocation support may be available for eligible employees.

Hiring process

• More detailed benefits information is provided during the hiring process.
• Background checks are administered in accordance with applicable law.
• Certain legal status requirements may apply under U.S. export control laws and regulations.