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FPGA Design Engineer (SystemVerilog)
Описание вакансии
Текст:
TL;DR
FPGA Design Engineer (SystemVerilog): Designing reusable FPGA RTL blocks for data handling and synchronization in complex communication networks with an accent on synthesizable SystemVerilog, clock-domain crossing prevention, and hardware validation. Focus on translating requirements into maintainable architectures, evaluating implementation trade-offs, and resolving integration issues across hardware, software, verification, and system engineering.
Location: Veldhoven, Netherlands
Company
develops semiconductor manufacturing technology and high-performance FPGA-based systems.
What you will do
- Design synthesizable SystemVerilog RTL blocks for data handling, synchronization, reset behavior, incomplete transfers, and software notifications.
- Define, document, negotiate, and verify requirements, including feasibility, rationale, and maintainability.
- Analyze architecture and implementation alternatives, perform trade-off studies, and align decisions with stakeholders.
- Document RTL architecture and behavior while identifying interface inconsistencies early.
- Collaborate with FPGA verification engineers, FPGA designers, software developers, hardware engineers, system architects, and integrators.
- Develop hardware tests, support product integration, contribute to technical roadmaps, and resolve technical issues.
Requirements
- Bachelor’s or master’s degree in electrical engineering, computer engineering, or a related technical field.
- At least three years of FPGA or digital RTL design experience.
- Strong hands-on experience with synthesizable SystemVerilog, including SystemVerilog interfaces.
- Understanding of synchronous digital design, clocking, resets, FPGA primitives, timing, and finite-state machines.
- Experience with FPGA simulation, linting, clock-domain crossing analysis, synthesis, implementation, and timing-analysis toolchains.
- Experience with digital communication, synchronization, networking, or comparable data-processing applications, plus Linux, Git, Python, and C.
Nice to have
- Experience with high-speed digital interfaces.
- Experience developing reusable FPGA RTL.
Culture & Benefits
- Work in a multidisciplinary engineering environment spanning architecture, implementation, verification, hardware, software, and system engineering.
- Contribute to reusable RTL blocks and complex, high-performance FPGA-based systems.
- Strong written and verbal communication in English is required.
- Access to controlled technology requires legal authorization under United States Export Administration Regulations before starting work.
- promotes an inclusive and diverse workplace and is an equal opportunity employer.