TL;DR

Dfx Validation Engineer: Design, code, and integrate DFT blocks into functional logic, ensuring high-quality integration with CPU architecture. Focus on DFT test content generation, HVM content development, and collaboration with post-silicon and manufacturing teams.

Location: On-site, Israel, Haifa

Company

%hirify_global% is responsible for driving business strategy and product development for %hirify_global%'s PC products and platforms.

What you will do

Design, code, simulate, and integrate DFT blocks (TAP, SCAN, MBIST, etc.) into functional logic.
Participate in defining CPU architecture and microarchitecture features to ensure DFT coverage.
Provide DFT test content generation and delivery to manufacturing.
Develop HVM content for rapid production ramp-up on automatic test equipment (ATE).
Verify DFT design features, resolve issues, and implement corrective measures for failing RTL tests.
Optimize logic to meet DPM and test-time goals.

Requirements

B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering.
At least 5 years of experience in hardware and logic verification or design.
Self and fast learner with good problem-solving capabilities.
Good communication skills and Fluent English (written and oral).

Nice to have

Experience with Post-silicon debug and content generation.
Scripting abilities (Perl/Python/Tcl) and Unix familiarity.
Design for Test (DFT) Flows, Tools, and Techniques.