Front End Design Verification Engineer (RISC-V)

Location: Remote, based in North America or Spain

Salary: $100,000–$500,000, including base and variable compensation targets.

Company

Tenstorrent develops high-performance AI computing platforms combining software, compilers, networking, and RISC-V semiconductor technology.

What you will do

• Verify the fetch unit and front end of next-generation high-performance RISC-V CPU cores.
• Develop verification strategies and sophisticated tests for instruction fetch, prediction, decode, and dispatch.
• Debug RTL and simulation failures using waveforms and standard simulation and debugging tools.
• Analyze corner cases involving speculative execution, branches, redirects, exceptions, and pipeline flushes.
• Collaborate with CPU architects, RTL designers, other design verification engineers, and software teams.

Requirements

• 6+ years of design verification experience with CPUs, SoCs, ASICs, or other complex digital designs.
• Strong experience with SystemVerilog and UVM, including constrained-random testing, assertions, functional coverage, and testbench development.
• Solid understanding of CPU architecture, including pipelines, instruction fetch and decode, branch prediction, speculative execution, or out-of-order execution.
• Experience debugging RTL and simulation failures with waveforms and standard tools.
• Strong programming skills in C, C++, and/or Python.
• Eligibility to access U.S. export-controlled technology is required; employment may depend on citizenship, permanent residency, or prior export-license approval.

Culture & Benefits

• Remote work from North America or Spain.
• Opportunity to work on processors for demanding AI, HPC, and high-performance computing workloads.
• Collaboration with CPU architects and RTL engineers.
• Competitive compensation and benefits package.
• Equal opportunity employment.