FPGA IP Software Development Engineer (FPGA Soft IP)

Location: Penang, Malaysia

Company

hirify.global develops FPGA Soft IP cores released through Quartus and Platform Designer for production FPGA designs.

What you will do

• Architect, design, and implement parameterizable FPGA Soft IP cores in VHDL, Verilog, or SystemVerilog.
• Own the complete Soft IP lifecycle, including RTL design, synthesis, simulation, lint, CDC analysis, STA, packaging, and example-design bring-up.
• Package IP for Quartus and Platform Designer, including metadata, HDL generation, parameter validation, and integration with Native PHY, transceiver, and interconnect IP.
• Define register maps, control interfaces, reset and clocking schemes, and user-facing data interfaces such as AXI-Stream and Avalon-ST.
• Build testbenches, assertions, regression suites, and coverage-driven tests for protocol compliance and configuration coverage.
• Collaborate with verification, firmware, software, and hardware teams; debug issues across simulation, synthesis, place-and-route, and FPGA hardware.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Electronic Engineering, Computer Engineering, Computer Science, or a related field.
• Four to six years of FPGA/ASIC RTL or Soft IP design experience, depending on degree level.
• Strong proficiency in parameterizable RTL using Verilog, SystemVerilog, and/or VHDL.
• Experience with synthesis, simulation, SDC timing constraints, CDC, STA, FPGA architecture, and the Quartus or equivalent vendor flow.
• Experience with IP catalog flows such as Platform Designer/Qsys or Vivado IP Integrator, plus AXI4, AXI-Stream, Avalon-MM, Avalon-ST, or CSR interfaces.
• Experience with Python, Tcl, and/or Perl automation, Git, structured code review, technical debugging, and cross-site collaboration.

Nice to have

• Experience with high-speed interface Soft IP such as JESD204B/C, Ethernet, PCIe, CPRI, Interlaken, or DDR.
• Experience with deterministic latency, multi-lane alignment, FEC, dynamic reconfiguration, or transceiver/Native PHY IP.
• SystemVerilog assertions, functional coverage, coverage-driven verification, UVM, EDA tools, and FPGA development-kit validation.
• Production Soft IP ownership, Quartus IP catalog releases, example designs, customer-facing documentation, mentoring, and technical leadership.

Culture & Benefits

• Regular full-time employment.
• Shift 1 schedule in Malaysia.
• Work is based in Penang and involves collaboration across sites.