Design Verification Engineer (SerDes)

Location: Remote from Iași, Romania

Company

hirify.global is an independent FPGA company developing programmable logic devices for data centers, telecommunications infrastructure, AI accelerators, and industrial systems.

What you will do

• Develop and maintain SystemVerilog/UVM verification environments for SerDes and PHY blocks.
• Write testbenches, functional coverage models, and assertions.
• Run simulations, analyze failures, and debug RTL and testbench issues.
• Verify high-speed SerDes IP used in PCIe, Ethernet, and other industry-standard interfaces.
• Collaborate with design, architecture, and analog teams on block-level and top-level verification.

Requirements

• BSc in Electrical Engineering, Computer Engineering, or an equivalent field.
• 0–5 years of experience in digital design or verification, including internships, academic projects, or industry experience.
• Working knowledge of SystemVerilog and basic familiarity with UVM concepts.
• Solid digital design fundamentals, including synchronous logic, FSMs, pipelining, and clock domain crossing.
• Strong analytical and debugging skills with the ability to investigate technical issues thoroughly.
• Good spoken and written English; candidates should preferably be able to reside in Iași.

Culture & Benefits

• Work remotely from Iași, Romania.
• Join a Design Verification team working on technically challenging silicon.
• Work alongside experienced engineers on silicon shipping to production.
• Build deep technical expertise in high-speed silicon verification with opportunities to learn, grow, and take ownership.
• Regular full-time employment on Shift 1 aligned with Romania.