Ph.D. Intern - Architecture, DSP & Systems Architecture (AI Infrastructure)

Location: Santa Clara, CA, United States

Salary: $31–$62 per hour

Company

hirify.global develops semiconductor solutions and data-infrastructure technologies for enterprise, cloud, AI, carrier, and hyperscale applications.

What you will do

• Architect, model, and evaluate system-level designs for switching, interconnect, and DSP applications.
• Develop and optimize DSP algorithms for high-speed optical and electrical links, including equalization, FEC, timing recovery, and signal integrity for PAM4 and coherent modulation.
• Design network architectures for AI fabrics, including forwarding pipelines, congestion control, traffic management, and load balancing.
• Build behavioral models and simulations in MATLAB, Python, or C++ to evaluate architecture, power, latency, and bandwidth tradeoffs.
• Collaborate with analog, digital, and software engineering teams to validate designs against hardware and silicon measurements.
• Present architectural proposals and algorithm results and contribute to technical documentation and design reviews.

Requirements

• Currently enrolled in a Ph.D. program in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Research focus in computer architecture, digital signal processing, communications systems, or networking.
• Research experience in processor or switch architecture, high-speed communications DSP, network protocols, or system-level modeling and simulation.
• Strong analytical fundamentals in areas such as signal processing, queuing theory, information theory, or computer architecture.
• Experience modeling and simulating complex systems using MATLAB, Python, or C/C++.
• Ability to communicate architectural decisions and algorithm tradeoffs clearly.

Nice to have

• Familiarity with Ethernet switching, programmable forwarding pipelines, congestion control, Ultra Ethernet Consortium protocols, RoCE, RDMA, SONiC, or P4.
• Experience with PAM4, coherent or high-speed serial-link DSP, including equalization, FEC, timing, and synchronization.
• Exposure to Verilog, SystemVerilog, cycle-accurate simulation, custom compute architecture, SoC design, or XPU/GPU interconnects.

Culture & Benefits

• Work on architecture and research problems connected to production-scale AI infrastructure and hyperscale data centers.
• Medical, dental, and vision coverage.
• Mental health resources, paid holidays, perks, and discounts.
• Additional compensation may be available for Ph.D. interns.
• Access to export-controlled technology may require an export license review under U.S. regulations.

Hiring process

• Interviews assess individual experience, thought process, and communication skills in real time.
• AI tools, transcription applications, automated answer generators, and note-taking bots are prohibited during interviews.