Lead Software Engineer - Logic Synthesis (C/C++)

Location: Shanghai, China

Company

hirify.global brings together technology leaders and innovators to solve complex challenges in the technology industry.

What you will do

• Develop and maintain the synthesizer for Palladium.
• Implement support for new VHDL and Verilog features.
• Optimize logic and improve synthesizer performance.
• Contribute to design modeling and collaborate across multi-site, multi-person projects.

Requirements

• Bachelor’s or master’s degree in electrical engineering, computer science, or computer engineering.
• 3–5 years of industry experience.
• Proficiency in C/C++ and operating system concepts.
• Experience with Verilog/SystemVerilog, VHDL, or SystemC design modeling.
• Good communication skills, attention to detail, and ability to work in multi-site projects.

Nice to have

• RTL modeling of bus functional models and exposure to UVM and SystemC/TLM verification methodologies.
• EDA/CAD tool development or logic design verification experience.
• Experience with AI tools such as Copilot or Claude Code.

Culture & Benefits

• Work on technology challenges described as impactful and difficult to solve.
• Collaborate with colleagues across multiple sites.