7 часов назад
Principal Digital Verification Engineer (mfd)
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Principal Digital Verification Engineer (mfd) (SystemVerilog/UVM): Leading verification of digital submodules, verification IPs, and testbenches across multiple integration levels with an accent on metric-driven verification, coverage, formal methods, and constrained-random testing. Focus on defining verification strategies and completion metrics, developing UVM testbenches, resolving hardware and software issues, and improving digital verification processes.
Location: Gratkorn, Austria
Company
operates in the electronic and semiconductor industry.
What you will do
- Own verification of digital submodules, verification IPs, and testbenches across different integration levels.
- Review subsystem and submodule requirements and design specifications for functional and technology increments.
- Define integrated verification strategies with subsystem architects and discipline leads, then break them into planned activities and tasks.
- Define verification metrics and methodologies for assessing campaign completion, including testbench component specifications.
- Track verification activities, maintain specifications and reports, and support project phase reviews.
- Collaborate with hardware, software, and system engineers to analyze and resolve issues, bugs, and support requests.
Requirements
- Master’s or PhD degree in Electrical/Electronic Engineering, Computer Science, or an equivalent field.
- At least eight years of professional experience in digital design and verification.
- Advanced knowledge of Verilog and SystemVerilog, with proven UVM testbench design and development experience.
- High proficiency in metric-driven verification, functional and code coverage, directed testing, and constrained-random methodologies.
- Advanced knowledge of formal verification methodologies and assertions; familiarity with ASIC/SoC design flows.
- Experience with Bash/tcsh, Tcl, Python, C, version control systems, and very good spoken and written English.
Nice to have
- Knowledge of VHDL.
- Training certifications in SystemVerilog and UVM methodologies from EDA vendors.
Culture & Benefits
- Collaborative and technically demanding working environment.
- Opportunities to follow courses, seminars, webinars, and technical literature on verification methodologies and tools.
- Home office and flexible working time.
- Meal benefits and additional employee benefits.
- Responsibilities may include security-related tasks and work within security certification scope, requiring a conscious and reliable working style.
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