Lead ASIC DFT Staff Engineer (ASIC DFT)

Location: United States

Salary: $70–$80 per hour

What you will do

• Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
• Drive scan architecture, scan insertion, scan-chain stitching, scan compression, ATPG generation, simulations, DRC analysis, and test-coverage closure.
• Own MBIST/LBIST integration, verification, silicon bring-up, failure analysis, diagnosis, and post-silicon debug.
• Develop DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
• Integrate JTAG, boundary scan, iJTAG, SSN, and IP-level DFT across RTL, synthesis, LEC, and physical-design flows.
• Collaborate with design, verification, physical design, STA, and silicon-validation teams; mentor DFT engineers and improve automation with TCL, Perl, or Python.

Requirements

• 10+ years of hands-on ASIC DFT experience with end-to-end ownership.
• Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, fault models, diagnosis, and test coverage.
• Experience with Synopsys, Cadence, and Siemens/Mentor EDA tools, including scan insertion, ATPG setup, simulation, debug, and DRC analysis.
• Strong understanding of PLLs, RTL design, synthesis, logical equivalence checking, physical-design implementation, and hierarchical DFT flows.
• Proven post-silicon debug and silicon bring-up experience across large SoC designs and multiple technology nodes.
• Role location: United States.

Nice to have

• SMS, Tessent, and SSN experience.
• MBIST post-silicon validation and DFT timing-closure support.
• Experience with yield learning, diagnosis, manufacturing-test optimization, and design-for-debug methodologies.