Эта вакансия в архиве
Посмотреть похожие вакансии ↓3 часа назад
SOC Static Timing Analysis Engineer
190 610 - 269 100$
Описание вакансии
Текст:
TL;DR
SOC Static Timing Analysis Engineer (SoC physical design and timing): Performing timing analysis and optimization for high-performance, low-power SoC designs with an accent on timing constraints, clock network design, and timing closure. Focus on resolving chip- and block-level timing violations, defining PVT conditions, and developing tools, flows, and methodologies for efficient physical design execution.
Location: Hybrid work model at an assigned site in Phoenix, Arizona, or Santa Clara, California, United States
Annual salary: $190,610–$269,100 USD
Company
develops computing and semiconductor technologies, including System-on-Chip designs.
What you will do
- Perform SoC-level static timing analysis and optimization to meet functional and performance requirements.
- Generate and verify timing constraints and resolve chip- and block-level timing violations.
- Conduct timing rollups and develop optimized clock networks for functionality, performance, and power efficiency.
- Define timing models, PVT conditions, and methodologies aligned with product plans and binning strategies.
- Collaborate with architecture, clocking, DFT, logic design, and full-chip design teams on integration and clock-network validation.
- Develop tools, flows, and methodologies that improve SoC physical design and timing processes.
Requirements
- Bachelor's degree in Computer Engineering, Computer Science, or a related STEM discipline with 6+ years of industry experience, or a master's degree with 4+ years of experience.
- 5+ years of experience in SoC-level static timing analysis, clock network design, and timing closure methodologies.
- Experience with timing constraint adaptation, physical design, and optimization techniques.
- Experience using industry-standard tools for timing analysis, extraction, and physical design.
- Experience with Tcl scripting and timing budgeting processes.
- Knowledge of DFT architecture is preferred.
Nice to have
- PhD in a related field with 3+ years of experience.
- Experience with high-performance physical design tools, flows, and methodologies.
- Experience with SoC clocking methodologies and digital design problem-solving.
- Experience collaborating across diverse design teams.
Culture & Benefits
- Hybrid work with time split between on-site work at an assigned site and off-site work.
- Competitive pay and stock bonuses.
- Health, retirement, and vacation benefits.